SED1796d 0b 1 ssc5000series pf935-01 SED1796d 0b n description the gate driver ic SED1796 is designed to drive an svga and xga display tft-lcd panel and enables capacity combining drive and punch-through voltage compensatory drive thanks to gate output voltage control. the maximum gate output voltage amplitude is 40v, enabling negative voltage output. it also enables double on gate drive, which outputs on twice in the same field during h reverse rotation drive. this ic has a built-in power supply circuit for the internal logic and you can select whether or not to use it. when using the circuit, no internal logic power needs to be supplied. the bump layout of this ic is designed for cog mounting, enabling a module architecture to be narrowed. n features l gate output voltage level: 4 values (v 1 to v 4 ) l gate output voltage amplitude: 40 v (max.) l low voltage operation available: 2.7 v (min.) l output shift direction-pin selection. l gate output voltage can be forcibly fixed thanks to the output enable function. l gate output negative voltage output available thanks to the level shift circuit. l double on gate drive available. l built-in internal logic power supply circuit. l package to be shipped l au bump chip l this product is not designed to resist radiation or light. tft lcd driver
2 SED1796d 0b n block diagram v 1l v ddhl v ss v eel v cc cpv v cc oe mode dio1 dio2 fr shl v 4l v 3l v 2l v 1r v ddhr v eer v l test ipc dr o154 o1 dl 156-bit gate output circuit level shifter control logic bi-direcrional shift register shifting level v 4r v 3r v 2r
SED1796d 0b 3 n bump layout chip size: 1.90 mm (x) 17.30 mm (y) chip thickness (reference): 0.625 mm (t) bump size: 80.0 m m (x) 100.0 m m (y) (nos. 1 to 39) 80.0 m m (x) 69.6 m m (y) (nos. 40 to 201) bump height (reference): 12.0 m m (typical) alignment symbol position: a = f 100 m m (764.0, 8460.0) and (764.0, C8460.0) b = f 50 m m (784.0, 8050.0) and (784.0, C8050.0) 40 20 1 b a 39 a b (0,0) x y
4 SED1796d 0b n absolute maximum ratings (v ss = 0 v) n recommended operating conditions (v ss = 0 v) parameter symbol rating unit supply voltage (1) v cc C0.3 to +7.0 v supply voltage (2) v ddh C0.3 to +45.0 v supply voltage (3) v ee C23.0 to +0.3 v supply voltage (4) v l v ee C0.3 to v ee +7.0 v supply voltage (5) v ddh C v ee C0.3 to +45.0 v supply voltage (6) v 1 C0.3 to v ddh + 0.3 v supply voltage (7) v 2 , v 3 , v 4 v ee C0.3 to v ddh +0.3 v supply voltage (8) v 1 Cv 4 C0.3 to +45.0 v input voltage v in C0.3 to v cc +0.3 v input current i in 10 ma output current i o 10 ma ambient operating temperature ta C25 to +85 c storing temperature t stg2 C55 to +125 c notes 1. all voltages refer to v ss unless otherwise specified. 2. the element may permanently break if used outside the absolute maximum ratings shown above. the element reliability may disadvantageously be affected if it is exposed to the absolute maximum rating conditions for a long time. 3. for voltages v ddh , v ee , v cc , v ss and v l , be sure to keep the condition of v ee v l v ss v cc v ddh . for voltages v 1 , v 2 , v 3 and v 4 , also be sure to keep the conditions of v ee v 4 , v 1 v ddh and v 4 v 2 , v 3 v 1 . 4. never float the logic system power supply while the high-voltage logic and gate output power supplies are turned on or allow v cc to go under 2.6 v, otherwise, the ic reliability may disadvantageously be affected. parameter symbol rating unit supply voltage (1) v cc +2.7 to +5.5 v supply voltage (2) v ddh +10.0 to +30.0 v supply voltage (3) v ee C20.0 to +5.0 v supply voltage (4) v l C16.0 to +0.5 v supply voltage (5) v ddh C v ee +15.0 to +40.0 v supply voltage (6) v 1 +8.0 to +30.0 v supply voltage (7) v 2 C20.0 to +10.0 v supply voltage (8) v 3 C20.0 to +20.0 v supply voltage (9) v 4 C20.0 to +10.0 v supply voltage (10) v 1 C v 4 +8.0 to +40.0 v operating frequency f cpv dc to 200 khz notes 1. ic operation is guaranteed within the recommended operating condition range. 2. insert a bypass capacitor for noiseproof measures near the power supply pin. 3. unless swinging the v 1 supply voltage, make the electric potential the same as that of v ddh . 4. when swinging the v 1 supply voltage, the guaranteed output resistance, rise and fall time ratings will differ. 5. when the output voltage during an output fixed period is 1 level only, make the v 2 electric potential the same as that of v 4 and fix fr at either the v cc or v ss level. 6. v ee + 4.0 (v) v l v ee + 5.5 (v)
SED1796d 0b 5 the recommended operating voltage is based on the combination of the high-dielectric strength logic system power supply conditions and the logic system power supply conditions (the hatched portion in the figure below). for the internal logic power supply, keep the condition of v ee + 4.0 (v) v l v ee + 5.5 (v). 0 10 40 [v] 20 15 30 35 ?0 v ee v ddh ? ee ?0 ? [v] v ddh 15[v] v ddh ? ee 40[v] v ee +4.0[v] v l v ee +5.5[v] 2.7[v] v cc 5.5[v] v ee v cc v ss 0[v] v l
6 SED1796d 0b n electrical characteristics under the recommended operating range l dc characteristics l ac characteristics ? input timing characteristics (ta = C25 to +85 c, v cc = 3.3 0.3 v, v ss = 0 v, v ddh = 30 v, v ee = C10 v, v l = C5 v) parameter symbol condition rating units pin used min. typ. max. l input voltage v il v ss v ss + 0.2 v all input pins (v cc C v ss ) h input voltage v ih v ss + 0.8 v cc v all input pins (v cc C v ss ) l output voltage v ol i ol = 40 m av ss v ss + 0.4 v dio1, dio2 h output voltage v oh i oh = 40 m av cc C 0.4 v cc v dio1, dio2 output resistance r on d v 1 = 0.5 v 0.73 1.47 k w o1 to o154 v 1 = 30 v, v 2 = 10 v, v 3 = 0 v, v 4 = C10 v input leakage current i li C1.0 +1.0 m a all input pins input capacity c in ta = 25 c 15 pf all input pins static current i cs (80) 250 m av cc consumption (1) static current i ds (45) 100 m av ddhl , v ddhr consumption (2) dynamic current i cc *1 (150) 300 m av cc consumption (1) dynamic current i l (30) 60 m av l consumption (2) dynamic current i ddh (75) 140 m av ddhl , v ddhr consumption (3) *1: svga display, 150 outputs, f dio = 65 hz, f cpv = f oe = 40 khz, output pin unloaded, double gate output (ta = C25 to +85 c, v cc = 3.3 0.3 v, v ss = 0 v, v ddh = 30 v, v ee = C10 v, v l = C5 v) parameter symbol condition min. max. unit cpv cycle t cpv 5.0 m s cpv high-level pulse width t cpvh 1.0 m s cpv low-level pulse width t cpvl 1.7 m s data setup time t ds 400 ns data hold time t dh 400 ns oe setup time t oes 0 (*2) *3 m s oe hold time t oeh 0.2 (*2) *3 m s *1: the input signal rise and fall times ( t r and t f ) are specified at 30 ns or less. *2: the values shown above will not apply when all oes are set at l. *3: t cpv applies unless all oes are set at h. *4: expected output waveform may not be obtained if the output load is large and the oe width is small.
SED1796d 0b 7 ? output timing characteristics cpv dio (in) on dio (out) oe t cpv t cpvh t dh t ds t oes t oeh t cpvl t pd2 t pd1 t pd3-2 t pd4 t pd3-1 t or t of 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 90% 90% 10% 10% 50% 50% (ta = C25 to +85 c, v cc = 3.3 0.3 v, v ss = 0 v, v ddh = 30 v, v ee = C10 v, v l = C5 v) parameter symbol condition min. typ. max. unit cpv to dio output delay time t pd1 c l = 20 pf 0.4 1.3 m s t pd2 0.47 1.3 m s cpv to on output delay time *1 v 3 ? v 1 t pd3-1 c l = 700 pf 0.68 1.2 m s v 4 ? v 3 t pd3-2 v 1 = 30 v, v 2 = 10 v 0.6 1.2 m s v 2 ? v 3 v 3 = 0 v, v 4 = C10 v oe to on output delay time v 4 ? v 1 t pd4-1 0.9 1.7 m s v 1 ? v 4 t pd4-2 0.54 1.0 m s on output rise time v 4 ? v 1 t or 1.44 2.2 m s v 2 ? v 1 on output fall time v 1 ? v 2 t of 1.2 1.8 m s v 1 ? v 4 *1: applies when all oes are set at l.
8 SED1796d 0b notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind aris ing out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no re presentation that this material is applicable to products requiring high level reliability, such as, medical products. morever, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material wil l be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject rel ating to strategic products under the control of the foreign exchange and foreign trade control law of japan and may require an export license from the min istry of international trade and industry or other approval from another government agency. ibm is registered trademark of international business machines corporation, u.s.a. ? seiko epson corporation 1996 all right reserved. electronic device marketing department ic marketing & engineering group 421-8 hino, hino-shi, tokyo 191, japan phone: 0425-87-5816 fax: 0425-87-5624 international marketing department i (europe, u.s.a.) 421-8 hino, hino-shi, tokyo 191, japan phone: 0425-87-5812 fax: 0425-87-5564 international marketing department ii (asia) 421-8 hino, hino-shi, tokyo 191, japan phone: 0425-87-5814 fax: 0425-87-5110 printed feb. 1998 in japan h
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